Layout Designer

This is Jr position., If you are meeting with below criteria means pls share your resume to karthik.ravichandran@hays.com.au with below details..

• Over all experience;
• Relevant experience;
• CCTC;
• ECTC;
• Current location;
• Will you able to attend final round in F2F at Bangalore;

Location; Bangalore

Role; Custom Standard Cell Design Engineer

Final round must be F2F.

Job Description

You will be responsible for the development of Arm custom standard cells in the latest, sub-3nm process technology nodes. You will work as part of a team that co-optimizes the circuit design with physical design engineers to improve the PPA of Arm cores that will be integrated into best-in-class SoCs.

You will work in close collaboration with the mask design team to provide optimally tuned layout, characterize and model all standard libra

Required Skills and Experience :

2+ years of relevant circuit design experience (for BSEE)

1+ years of relevant circuit design experience (for MSEE)

Experience in the identification, design and verification of cells specifically targeted to improve core and SoC level PPA

In-depth understanding of MOSFET electrical characteristics, transistor level device physics, PPA trade-offs, layout and variability especially at 3nm and below technology nodes

Expertise in transistor level design of static circuits including state retaining elements such as latches and flops

Hands-on development of standard cell EDA view characterization, modeling and QA

Experience with standard cell characterization tools and Spice circuit simulators

Familiarity with scripting languages such as Perl or Python

Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems

Demonstrate a positive attitude and respect for all members of the team

Be motivated to continuously develop skills and accept various responsibilities as a part of contributing to Arm’s success

Ability to analyze data and present conclusions effectively

An engineer with

1–4 years of experience in standard cell or custom circuit design , strong knowledge of

CMOS device physics

and

transistor-level design , and hands-on expertise in

SPICE simulation

and

cell characterization tools

like

Cadence Liberate

or

Synopsys SiliconSmart . Skilled in

Python / Perl scripting , familiar with

advanced process nodes (≤5nm) , and capable of

PPA optimization

through close collaboration with layout and physical design teams.