Leadsoc Technologies - Senior Design Verification Engineer - SoC

Role Overview :

We are hiring an experienced SoC Design Verification (DV) Engineer to join our verification team. The ideal candidate will drive verification efforts for complex SoC blocks using SystemVerilog and UVM, work with high-performance buses and GPU subsystems, and collaborate closely with RTL, architecture, and validation teams to deliver silicon-quality designs.

Role & Responsibilities :

• Lead and execute functional verification for SoC subsystems and IP blocks.
• Develop, maintain, and extend UVM-based verification environments for AXI / APB interconnects, GPU interfaces and SoC integration points.
• Write SystemVerilog testbenches, assertions (SVA), coverage models, scoreboards, and checkers.
• Plan verification strategy : define test plans, coverage goals (functional / statement / functional coverage), directed + randomized tests, and regression suites.
• Debug RTL and simulation failures; perform root-cause analysis and work with RTL designers to close issues.
• Integrate and run regressions on simulators (e.g., VCS / Xcelium / Simulator of choice) and debug with waveform tools.
• Collaborate with architects, RTL designers, and firmware teams for system-level verification and bring-up support.
• Contribute to automation of regression runs, CI pipelines, and reporting.
• Mentor junior DV engineers and review verification code for quality and reusability.
• Prepare verification sign-off reports and help with DV metrics tracking.

Must-Have Skills & Knowledge :

Good-to-Have / Desirable :

What We Offer :

(ref : hirist.tech)