Analog Engineer- Layout

About the Company

We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision. This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.

Job Description – Senior Analog Layout Engineer (8 to 17 Years Experience)

Position : Senior Analog Layout / IP Delivery Engineer

Experience Required : 8+ Years

Location : Hyderabard / Remote

Company : Spintronics AI Semiconductors

Role Overview

We are seeking a highly experienced Senior Analog Layout Engineer with strong expertise in chip-level handling of high-speed analog IPs, deep understanding of ICC2-based top-level integration, and the ability to independently run block-level simulations.

The candidate must have very strong IP verification knowledge and experience coordinating with foundry teams for signoff, tape-out, and model-related interactions. This role requires full ownership of IP development, verification, integration, and delivery.

Key Responsibilities

• Handle chip-level planning and integration of high-speed analog IPs
• Perform complete analog layout design including floorplanning, routing, matching, shielding, EM / IR checks, and parasitic optimization.
• Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.
• Strong understanding of ICC2 flows for complete SoC / top-level integration.
• Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.
• Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.
• Work closely with foundry teams for :
• PDK clarifications
• LVS / DRC rule updates
• Model issues and PEX rule discussions
• Tape-out requirements and signoff guidelines
• Coordinate with PD, DV, circuit design, and packaging teams for smooth IP-level delivery.
• Prepare and deliver IP documentation, abstracts, verification reports, and GDS.
• Mandatory experince in TSMC 5NM.

Required Skills

o IP-level verification

o DRC / LVS / ERC

o PEX / RC extraction

o Signoff decks & reliability checks

Good to Have

Pay range and compensation package

Location : Remote / India (must support USA / Canada time zone)

Travel : Willing to travel to the U.S. for project release (as required)

Equal Opportunity Statement

We are committed to diversity and inclusivity.