Senior Engineer II - Design Engineer

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Job Description:

As a Design Engineer in the FPGA Business Unit, you will lead the design and development of advanced FPGA-based solutions and SoC components. This role demands strong technical leadership, deep expertise in RTL design, and hands-on experience across the full chip lifecycle—from microarchitecture definition to post-silicon validation. You will collaborate with global teams to deliver high-performance, power-efficient designs for next-generation FPGA products

Key Responsibilities:

• Architecture & DesignDefine and develop microarchitecture specifications for FPGA subsystems and SoC components.Perform RTL design in Verilog/SystemVerilog for datapath and control logic.Drive design for performance, power, and area optimization.
• Integration & VerificationIntegrate complex IP blocks and subsystems into FPGA fabric and SoC-level designs.Collaborate with verification teams to develop test plans and debug pre-silicon and post-silicon issues.
• Prototyping & EmulationDevelop RTL for FPGA-based prototyping and emulation for early validation of SoC designs.Support hardware bring-up and debug using oscilloscopes, logic analyzers, and FPGA platforms.
• Post-Silicon DebugParticipate in silicon validation, characterization, and debug activities.Develop strategies for hardware/software co-validation and system-level performance tuning.
• Cross-Functional CollaborationWork closely with architecture, software, and product teams to align design goals with system requirements.Mentor junior engineers and promote best practices in design methodology.

Requirements/Qualifications:

Required Qualifications

• Education: BSEE/MSEE (preferred) in Electrical/Electronics/VLSI Engineering.
• Experience: 8 to 12 years in ASIC/FPGA design, with at least 5 years in technical leadership roles.
• Core Skills:Experience in digital design with strong RTL coding skills in Verilog/SystemVerilog.Excellent understanding of SoC architecturesExperience in integration of complex IPs in SoC .Excellent understanding of low power design techniques and methodologies.Experience in running all the static RTL checks – Lint, CDC.Good understanding of synthesis, STA, timing closure, and ECOsFamiliarity with FPGA design tools (Xilinx Vivado, Intel Quartus, Lattice Diamond).Solid understanding of SoC integration, AXI/AMBA bus protocols, and low-power design techniques.Proficiency in configuration and integration of components like DDR, Ethernet, USB, PCIe..

Desirable Skills

• Protocols & Domains:PCIe Gen4/Gen5, DDR4/DDR5, LPDDR4X, MIPI DSI/CSI, Ethernet MAC, USB.Security and cryptography IP integration.ARM/RISC-V architecture.
• Advanced Capabilities:Exposure to post-silicon debug, emulation, and hardware prototyping.Experience with FPGA-based acceleration platforms and simulation/emulation flows.
• Software & Scripting:Python, TCL/TK, and C/C++ for automation and validation.
• Tools:Familiarity with Cadence/Mentor simulation suites and revision control systems (Git, Perforce).

Preferred Attributes

• Strong analytical and problem-solving skills.
• Ability to lead cross-site teams and manage complex design programs.
• Excellent communication and collaboration skills for global team interaction.

Why Join Us?

• Work on cutting-edge FPGA and SoC technologies shaping next-generation computing.
• Opportunity to lead methodology innovation with AI/ML-driven verification flows.
• Collaborate with global teams and impact first-silicon success for flagship products.

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