Strong experience with SystemVerilog, UVM, and object-oriented testbench development.
In-depth knowledge of NoC protocols (AXI4, CHI, TileLink, or proprietary NoC).
Verification experience with coherent interconnects, cacheable traffic, and memory subsystem validation.
Familiarity with Synopsys, Cadence, or Siemens verification tools (VCS / Xcelium / Questa).
Familiarity with formal verification, assertions (SVA / PSL), and coverage metrics.
Ability to debug low-level issues using waveform analysis, scoreboards, and transactors.
Familiarity with multi-core CPU, DSP, or GPU interconnect systems is a plus.
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Lead Verification Engineer • India
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