Application Specific Integrated Circuit Design Engineer

Role - Senior ASIC / SoC RTL Engineer / LeadExperience - 5+ yearsLocation - Hyderabad, Bangalore, Pune and KochiNotice Period - Immediate to 60 daysJD of Senior ASIC / SoC RTL Engineer / LeadExpertise in SoC subsystem / IP designExpertise in IP design, Subsystem / Cluster and SoC level integration using Verilog / System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge of synthesis and low power is a plusGood understanding of AMBA bus protocols (AXI, AHB, ATB, APB)Good understanding of timing conceptsKnowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPIExpertise in setting up and using tools like a. Spyglass Lint / CDC b. Synopsys DC c. Verdi / XcelliumUnderstanding of scripting languages like Make flow, Perl ,shell, python etcUnderstanding of processor architecture and / or ARM debug architecture is a plusAble to help and debug issues for multiple subsystemsAble to create / review design documents for multiple subsystemsAble to support physical design, verification, DFT and SW teams on design queries and reviews