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Senior Design Verification Engineers

ConfidentialHyderabad / Secunderabad, Telangana

30+ days ago

Job description

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM).

Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development.

Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment.

Driving the deployment and smooth execution of SLM solutions into customers projects.

Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have :

Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution.
Driving the adoption of Synopsys SLM solutions at premier customer base worlwide.
Influencing the development of next-generation SLM IPs and solutions.

What You ll Need :

BSEE / MSEE in Electrical Engineering, Computer Engineering, or related field.
4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both.
Good knowledge of AXI, APB
Background in verification, with at least sub-system level verification
Debugging abilities to identify issues in functional verification.
Knowledge of DMA, ideally should have verified a sub-system with DMA
Knowledge of High-speed IO sub-systems like PCIe and USB
A thorough understanding of memory mapping concepts is essential.
End to end knowledge of how transactions / data flow between the HSIO interface to / from memory
Knowledge and experience with Memory BIST / DFT / ATE / SLT / any other test solutions
Ability to evaluate technical suggestions from customers and work with internal teams (product management / R&D) to make decisions
Customer facing experience is a plus - educating / guiding customer on technical details of a solution
Good to have :
Hands-on debug experience of silicon is a plus
Some programming experience to write / debug simple drivers in C
Detailed knowledge of the PCIe and USB protocols
Architecture / micro-architecture experience
Working with FPGAs

Skills Required

SoC-level functional verification, Design-for-Test (DFT), AXI and APB protocols, high-speed IO subsystems (PCIe, USB), Memory BIST and test solutions

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Senior Design Verification Engineer • Hyderabad / Secunderabad, Telangana