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ASIC RTL Design Engineer

ASIC RTL Design Engineer

ACL DigitalDelhi, IN
10 hours ago
Job description

ASIC RTL Design Engineer

Location : Bangalore

Job Description : Skills & Experience :

  • 3-5 years of experience in ASIC front end design and quality check.
  • Strong fundamental knowledge of digital design, Verilog, and scripting language.
  • Experience in multiple clock and voltage domain design.
  • Working knowledge for FE flows like Lint, CDC, synthesis, and other quality checks.
  • Understanding of UPF and experience in low power checks is preferred.
  • Understanding of memory controller and / or cache controller and / or memory subsystem is add-on.
  • Must possess good communication skills; prior experience working with global teams is desirable.
  • MTech / B.Tech / BE - Electronics

Responsibilities :

  • RTL Front-end quality checks – Lint, CDC, synthesis, LEC, low power checks.
  • Write and debug constraints for above QA flows.
  • Work with subsystem and / or SOC integration team on design integration and debugs.
  • Work with cross functional teams to ensure smooth and on-time execution.
  • Provide support to sub-system, SoC integration and synthesis, DFT, post-silicon debug.
  • Work with global team at different time zones
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