ASIC Design Lead

Position : Senior ASIC RTL Design Engineer

Experience : 10+ Years

Location : Hyderabad

Work Mode : Work From Office

Job Description :

We are seeking a highly skilled Senior ASIC RTL Design Engineer with strong expertise in Verilog / SystemVerilog RTL coding and deep knowledge of digital design concepts. The ideal candidate must demonstrate excellent debugging skills and the ability to handle complex SoC / ASIC architectures. In this role, you will lead RTL development, optimize design for performance, power, and area, and work closely with verification, architecture, and physical design teams to ensure high-quality deliverables. This is a full-time office-based position offering the opportunity to drive innovation and mentor junior engineers in cutting-edge semiconductor projects.

Apply if you :

– Have 10+ years of ASIC RTL experience

– Excel in RTL coding & debugging

– Prefer a collaborative, office-based work environment