Job Title : Physical Design Engineer
Experience : 4+ Years
Location : Banglaore / Hyderabad
Employment Type : Full-time
Industry : Semiconductors / VLSI / ASIC Design
Job Summary :
We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.
Key Responsibilities :
- Own block-level or full-chip implementation from RTL to GDSII.
- Perform :
- Floorplanning and placement
- Clock tree synthesis (CTS)
- Routing and optimization
- Run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks.
- Drive physical verification and signoff across various corners and scenarios.
- Collaborate with RTL, DFT, STA, and power teams for successful integration.
- Implement and debug low-power design techniques (UPF / CPF-based flows).
- Apply congestion analysis, ECOs, and timing fixes across critical paths.
- Optimize for performance, power, and area using EDA tools and foundry guidelines.
- Prepare design reports and support tapeout activities.
Required Skills and Experience :
B.E / B.Tech or M.E / M.Tech in Electronics, Electrical, or VLSI Design.4+years of experience in ASIC physical design.Strong hands-on experience with tools like :Place & Route : Cadence Innovus, Synopsys IC Compiler II (ICC2), Siemens NitroSTA : Synopsys PrimeTimeSignoff : Calibre (DRC / LVS), RedHawk (IR / EM), TempusGood understanding of physical design concepts : floorplan, placement, CTS, routing, ECO, and signoff.Familiarity with scripting languages : Tcl, Perl, Python for flow automation.Solid grasp of timing analysis, power grid design, and physical verification flows.Interested can share Cv to Sharmila.b@acldigital.com