Physical Design Lead - Static Timing Analysis

Role : Physical Design Lead

Experience : 6 to 15 Years

Location : Bangalore / Hyderabad / Kochi / Pune

Requirement :

• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl / Tk / Perl.
• Must have hands-on experience on Synopsys / Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre).
• Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environment
• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl / Tk / Perl
• Well versed with timing constraints, STA and timing closure.

Location : Bangalore / Hyderabad / Kochi / Pune

(ref : hirist.tech)