Job Title : DFT Engineer (Senior / Lead)
Location : Bengaluru, KA
Experience : 10–15 Years
We are looking for a highly experienced DFT Engineer with strong expertise in Mentor Graphics Tessent tools. The candidate should have deep hands-on experience across the full DFT flow—implementation, validation, debug—and be able to work independently on complex SoC designs.
Key Responsibilities
- Perform RTL insertion , DFT DRC checks , and debug using Tessent tools.
- Execute scan insertion , ATPG pattern generation , and coverage validation .
- Conduct gate-level simulation (GLS) debug, including timing-enabled GLS .
- Generate and validate MBIST patterns for memory test.
- Independently debug and resolve DFT issues across the SoC.
- Collaborate with cross-functional engineering teams to address design and test challenges.
- Ensure high quality and coverage of DFT implementation.
Essential Requirements (Must-Have)
10–15 years of DFT experience with strong hands-on expertise in Tessent (RTL insertion, DRC, debug).Proven experience in scan insertion , ATPG , and GLS debug .Strong knowledge of MBIST pattern generation and validation.Solid understanding of timing-enabled GLS and related debug flows.Excellent problem-solving and debugging skills.Ability to work independently with minimal supervision.Strong communication skills for cross-team collaboration.