Manager - Memory IP Design Engineering

Description :

Role : Manager Memory IP Design Engineer (eFuse / MTPM / OTP / MRAM / SRAM)

Location : Bengaluru, India

Experience : 1215 years

Qualification : M.Tech in Electrical / VLSI / Microelectronics or related field

About the Role :

We are seeking a highly motivated and experienced Memory IP Design Engineer (Manager level) to join our global semiconductor design team.

The ideal candidate will have deep expertise in custom memory design, simulation, and verification, with proven hands-on experience across NVM technologies such as eFuse, MTPM, OTP, MRAM, and SRAM.

Youll collaborate closely with design, layout, technology, test, and product engineering teams to deliver high-quality, high-reliability memory IPs with optimized cycle time and performance.

Key Responsibilities :

• Lead circuit design, simulation, and characterization of full-custom memory circuits.
• Conduct functional simulations, statistical analysis, and timing characterization.
• Manage sign-off and release of memory IPs on dedicated validation test chips.
• Support silicon bring-up and post-silicon characterization.
• Participate in design and layout reviews, ensuring design quality and efficiency.
• Drive innovation and continuous improvement in design methodologies.
• Collaborate across global, multi-disciplinary teams for successful project execution.

Required Skills & Experience :

Preferred Qualifications :

(ref : hirist.tech)