Lead ASIC Digital Design Verification (Full Chip & IP Verification)

You Are:

You are a highly motivated and detail-oriented verification engineer with a passion for ensuring the functionality and reliability of advanced semiconductor technologies. You possess a strong background in digital verification and have a keen understanding of analog and mixed-signal (AMS) verification flows. With 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development, you bring expertise in areas such as Digital Verification, AMS Verification with Verilog A, and RNM (Real Number Modeling). You thrive in a collaborative environment, working seamlessly with cross-functional teams to achieve top-level integration and verification goals. You are committed to continuous learning and eager to take on technical leadership roles, guiding teams to intercept TQV and other swim lanes for top-level integrations. Your knowledge of System Verilog, foundry PDKs, and SOC Design flow sets you apart, and you are ready to contribute to the success of Synopsys' Sensor IP business unit.

What You'll Be Doing:

• Leading the digital verification flow for PVT Sensor Digital Verification.
• Setting up and managing AMS Verification and front-end Integration for MSIPs.
• Developing and supporting next-generation analog, digital, and mixed-signal IPs.
• Ensuring all blocks are verified for behavioral and functionality from top-level integration.
• Collaborating with a team to intercept TQV and other swim lanes for top-level integrations.
• Implementing mixed-mode simulations with significant improvements in execution time.

The Impact You Will Have:

• Enhancing the reliability and performance of semiconductor lifecycle management solutions.
• Accelerating the integration of intelligent in-chip sensors and analytics capabilities.
• Optimizing performance, power, area, schedule, and yield for cutting-edge technology products.
• Reducing risk and time-to-market for differentiated products.
• Contributing to the development of Synopsys' next-generation analog, digital, and mixed-signal IPs.
• Supporting the growth and success of Synopsys' Sensor IP business unit.

What You'll Need:

• BS or MS degree in Electrical Engineering, Computer Science, or Computer Engineering.
• 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development.
• Expertise in Digital Verification and/or AMS Verification with Verilog A and RNM.
• Proficiency in System Verilog and RNM (Real Number Modeling).
• Understanding of latest foundry PDKs and their usage in FE & BE flows.

Who You Are:

• A detail-oriented and highly motivated verification engineer.
• A collaborative team player with excellent communication skills.
• A continuous learner eager to stay updated with industry trends and technologies.
• A leader capable of guiding and mentoring teams to achieve verification goals.
• A problem-solver with strong analytical and debugging skills.

Skills Required
Debugging, Uvm, systemverilog