DV Engineer

Role : Design Verification Engineer

Experience : 4-10 Years

Location : BNG

Job description

General Summary :

• Strong knowledge of digital design and SOC architecture.
• Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM / OVM & System C
• Experience in HDL such as Verilog
• Knowledge of ARM / DSP CPU architecture, High Speed Peripherals like USB2 / 3, PCIE or Audio / Multimedia
• Familiarity with Power-awareVerification, GLS, Test vector generation is a plus
• Exposure to Version managers like Clearcase / perforce
• Scripting language like Perl, Tcl or Python
• Analytical and Debugging skills

Minimum Qualifications :