Principal RTL Design and Verification Engineer

Hi All,

Eximietas Design Hiring Senior RTL Design ( Micro-architecture ) Architects / Sr. Manager.

Experience : 8+ Years.

Location : Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.

Anyone with a Valid H1B or Already in US.

❖ Minimum Qualifications : Bachelor's degree in Computer Science, Electrical / Electronics.

❖ Engineering 8+ years of ASIC SOC RTL ( Micro-architecture ) experience.

❖ ARM Processor Integration Preferably M55 is a Must.

❖ Strong understanding of design concepts.

❖ ASIC flow Understanding of SDC Understanding STA reports.

❖ Understanding of CDC logic Knowledge of lint rules and exceptions.

❖ Design and use of block level simulations to bring up IP.

❖ Knowledge of AMBA buses and when to use them.

❖ Knowledge on common processor architectures (ARM, RiscV).

❖ FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.

❖ Relevant tool experience such as : Socrates, Core Consultant in addition to standard simulation tools (xcellium, vcs, etc) JTAG debugging experience (Coresight, Lauterbach, etc).

❖ Low power design techniques / UPF As an RTL Engineer, Candidate will be responsible to work at IP, Subsystem, or SoC-related tasks.

Responsibilities :

❖ Collaborate with architects, pre- and post-silicon verification teams to meet deadlines.

❖ Coordinate with customer leads, ensuring all deliverables and timelines are met.

Interested Engineers, please share your updated resume : maruthiprasad.e@eximietas.design