Lead Memory Design Engineer

𝗟𝗲𝗮𝗱 𝗠𝗲𝗺𝗼𝗿𝘆 𝗗𝗲𝘀𝗶𝗴𝗻 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿

𝗥𝗲𝘀𝗽𝗼𝗻𝘀𝗶𝗯𝗶𝗹𝗶𝘁𝗶𝗲𝘀 :

As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.

𝗥𝗲𝗾𝘂𝗶𝗿𝗲𝗱 𝗦𝗸𝗶𝗹𝗹𝘀 𝗮𝗻𝗱 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲 :

🔸 Understanding of computer architecture and concepts.

🔸 Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations.

🔸 Good experience in design verification : Sense amplifier analysis, self-time analysis and marginality analysis.

🔸 Understanding of high speed / low power CMOS circuit design, clocking scheme, Static and complex logic circuits.

🔸 Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.

🔸 Strong knowledge of physical implementation impact on circuit performance.

🔸 Good understanding of high-performance and low power circuit designs with exposure to FinFet technologies, bitcell stability analysis

🔸 Proven experience as the designated responsible individual for a memory design, leading a small team of designer.

𝗘𝘅𝗽𝗲𝗰𝘁𝗲𝗱 𝘁𝗼 𝗵𝗮𝘃𝗲 𝗴𝗼𝗼𝗱 𝗶𝗻𝘁𝗲𝗿𝗽𝗲𝗿𝘀𝗼𝗻𝗮𝗹 𝘀𝗸𝗶𝗹𝗹𝘀.

🔸 Circuit Design : Design and develop digital circuits for memory blocks like SRAM, register files, and caches.

🔸 Simulation and Verification : Perform simulations and verification to ensure functionality and optimize for power, performance, area, timing, and yield.

🔸 Minimum 7 Yrs of experience in SRAM / memory design Margin, Char and its related quality checks.

𝗡𝗶𝗰𝗲 𝗧𝗼 𝗛𝗮𝘃𝗲 𝗦𝗸𝗶𝗹𝗹𝘀 𝗮𝗻𝗱 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲 :

🔸 Some Experience of working on Cadence or Synopsys flows.

🔸 Experience with Circuit Simulation and Optimization of standard cells.

𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲 : 𝟴 𝘁𝗼 𝟭𝟱 𝗬𝗲𝗮𝗿𝘀

𝗡𝗼𝘁𝗶𝗰𝗲 𝗣𝗲𝗿𝗶𝗼𝗱 : 𝟯𝟬 𝘁𝗼 𝟵𝟬 𝗗𝗮𝘆𝘀

𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻 : 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲

𝗔𝗯𝗼𝘂𝘁 𝗖𝗼𝗺𝗽𝗮𝗻𝘆

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