Design Integrity Engineer

Standard Cell Design Engineer Company Overview : M31 Technology Corporation is a leading provider of silicon intellectual property (IP) solutions, headquartered in Hsinchu, Taiwan. With extensive expertise in IP development, IC design, and electronic design automation, M31 delivers world-class solutions in high-speed interface IPs, memory compilers, and standard cell libraries. For more information, please visit Position : Staff Standard Cell Design Engineer Location : Bengaluru, India Employment Type : Full-time | On-site Role Summary M31 Technologies India Private Limited is seeking an experienced Standard Cell Design Engineer to join our dynamic team in Bengaluru. The role involves designing and developing advanced standard cell libraries for cutting-edge FinFET technology nodes such as 4nm, 3nm, and 2nm. The ideal candidate will bring strong technical depth in circuit design, PPA optimisation, and cell architecture development, working collaboratively with global teams to deliver best-in-class IP solutions for next-generation SoCs. Key Responsibilities Design and develop complex combinational and sequential standard cells optimised for power, performance, and area (PPA). Collaborate with EDA vendors to enable and validate new synthesizable cell architectures. Enhance library architectures and optimise designs for lower FinFET nodes (3nm, 2nm). Analyse reliability, high-sigma, and timing sign-off parameters to ensure high-yield tape-outs. Work closely with implementation teams (STA, P&R) to debug and improve critical path performance. Contribute to test chip design, silicon validation, and data correlation activities. Apply low-power and high-speed design techniques to achieve performance targets. Develop and maintain automation flows using Perl, Python, or TCL scripting. Provide technical guidance and mentorship to junior design engineers. Required Qualifications 5+ years of experience in standard cell circuit design across FinFET technologies. Proven expertise in combinational and sequential cell development. Strong understanding of PPA optimisation, design sign-off, and library characterisation. Hands-on experience with EDA tools for layout, timing, and simulation (Cadence, Synopsys, or equivalent). Sound knowledge of STA, place-and-route, and timing closure methodologies. Excellent problem-solving, analytical, and collaboration skills. Bachelor’s or Master’s degree in Electrical or Computer Engineering, preferably with a focus on VLSI design. Preferred Qualifications Experience working on FinFET nodes (4nm and below). Knowledge of reliability and high-sigma design techniques. Familiarity with CPU or GPU standard cell design. Proficiency in automation and scripting (Perl, Python, TCL). Advanced degree (MTech / PhD) in Electrical or Computer Engineering .