Design for Test Engineer

Hi

We’re looking for someone who can walk into a complex SoC environment, take charge of the entire DFT strategy, and push it all the way through silicon. If you enjoy solving hard testability problems, obsess over coverage numbers, and like working across design, PD, and test teams, this role will suit you well.

What you’ll handle

• Lead DFT architecture, planning, and execution for mid to large-scale SoCs.
• Build and integrate scan, MBIST / LBIST, boundary scan (IEEE 1149.1 / 1500), and compression flows.
• Own ATPG generation, coverage analysis, and drive yield and defect-escape improvements.
• Work hands-on with Tessent, DFTAdvisor, SpyGlass-DFT, ATPG, and fault simulation tools.
• Perform RTL and gate-level DFT insertion with an eye on timing, area, and power trade-offs.
• Support silicon bring-up, ATE vector debug, and post-silicon diagnostics / failure analysis.
• Write clean RTL (Verilog / SystemVerilog) and maintain solid fundamentals in STA.
• Use scripting (TCL / Python / Perl) to automate, optimize, and strengthen DFT flows.
• Partner with design, PD, and ATE teams and produce clear, reliable documentation.