Lead STA Engineer

About Us :

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM / HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com.

Job Overview

Job Description :

We are seeking a highly skilled and experienced Lead STA (Static Timing Analysis) Engineer to join our team in Bangalore. The ideal candidate will have deep expertise in timing closure for high-speed designs and hands-on experience with Synopsys timing tools.

Key Responsibilities :

Lead STA efforts for complex SoC designs at advanced nodes (3nm and below)

Perform timing analysis and closure using Synopsys PrimeTime and FusionCompiler

Work on high-speed interfaces including 100G Ethernet and PCIe Gen6

Collaborate with design, physical implementation, and verification teams to resolve timing issues

Develop and maintain timing constraints and methodologies

Ensure timing sign-off quality and compliance with project requirements

Required Skills & Experience :

8–12 years of experience in Static Timing Analysis

Strong hands-on expertise with Synopsys STA tools (PrimeTime, FusionCompiler)

Proven experience in high-speed SERDES designs (GHz+ frequencies)

Familiarity with TSMC 3nm or similar advanced process nodes (preferably 5nm and below)

Solid understanding of digital design, timing constraints, and physical design flow

Excellent problem-solving and communication skills