Memory Layout Engineer

Job Title : Memory Layout Engineer

Experience : 3+yrs

Location : Bangalore

Job Type : Full-time

Industry : Semiconductors / VLSI / Memory Design

Job Summary :

We are looking for a Memory Layout Engineer with strong expertise in physical layout design of memory components such as SRAM, ROM, Register Files, or custom memory IPs. The candidate will be responsible for delivering high-quality, DRC / LVS-clean layouts optimized for performance, area, and power.

Key Responsibilities :

• Design full-custom layouts for memory components like SRAM, ROM, CAM, Register Files, or sense amplifiers.
• Work closely with circuit designers to understand schematics and translate them into optimized layouts.
• Floorplanning, transistor-level placement, routing, and matching to meet electrical and physical design constraints.
• Run physical verification (DRC, LVS, ERC, antenna checks) using industry-standard tools.
• Perform parasitic extraction (PEX) and assist in post-layout simulation.
• Ensure layouts meet design rules for process technologies (e.g., 5nm, 7nm, 16nm, 28nm).
• Implement design automation using SKILL, Python, or Tcl where applicable.
• Work with cross-functional teams (circuit, verification, CAD) to meet project milestones.

Required Skills and Experience :

Preferred Qualifications :

Why Join Us?

Interested can share Cv to Sharmila.b@acldigital.com