Designing and optimizing standard cell libraries to achieve targeted PPA.Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells.Collaborating with layout designers to optimize layout parasitics.Engaging in layout extraction and understanding layout-dependent parameters.Conducting timing and power characterization of standard cells.Working closely with cross-functional teams for optimization across the design chain.The Impact You Will Have :
- Enhancing the performance, power, and area of standard cell libraries.
- Contributing to the development of high-impact, cutting-edge technology.
- Driving innovation in complex circuit design and optimization.
- Ensuring the successful integration of IP blocks into SoCs.
- Influencing the design and development of self-driving cars, AI, and IoT devices.
- Supporting Synopsys leadership in the silicon IP market.
What You ll Need :
- Bachelors or Masters degree in Electrical Engineering or related field.
- 3+ years of experience in standard cell library design.
- Expertise in CMOS device characteristics and submicron process nodes.
- Proficiency in designing complex circuits and running high sigma variation analysis.
- Experience in layout design and optimization.
Who You Are :
- Strong analytical and logical thinker.
- Detail-oriented with excellent problem-solving skills.
- Effective communicator and collaborator.
- Innovative and passionate about technology.
- Adaptable and able to work in a dynamic, fast-paced environment
Skills Required
Standard cell library design, complex circuit design (flip-flops, level shifters, etc.), CMOS device knowledge, layout optimization and parasitic extraction