SystemVerilog Verification Engineer

Lead Design Verification - NOC

Experience : 7 years

Location : Bangalore

Key Responsibilities :

• Develop UVM-based verification environments for NoC / IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.
• Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.
• Integrate and verify IPs like AXI4, CHI-B / C / E, PCIe, and UCIe connected via NoC.
• Model and validate credit-based flow control, packet routing, QoS, and virtual channel behavior.
• Perform assertion-based verification (SVA / DVL) for protocol compliance and corner cases.
• Debug complex interactions at simulation or emulation level, including deadlocks, congestion, or ordering violations.
• Work closely with architects and RTL teams to align verification coverage and performance metrics.
• Perform coverage closure (code + functional) and ensure complete verification sign-off.

Required Skills :

Interested,please share your updated resume to janagaradha.n@acldigital.com