Physical Design Lead
Location : Bangalore
We are a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships.
We are a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.
Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services.
Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.
We are looking for an experienced SOC Physical Design Manager and deliver the next generation of cutting-edge graphics designs Role includes managing a team of 10+ members.
KEY RESPONSIBILITIES :
- Manage the team responsible for Synthesis, Physical Design, timing and Physical closure
- Manage a large team of internal and external resources
- Responsible for ensuring the completion of the SOC chip on schedule with high QOR
- Physical implementation of block level and subsystem level
- Contribute to Synthesis, Power Reduction, Timing Convergence Floorplan efforts of block and subsystem
PREFERRED EXPERIENCE :
Proven track record on successfully managing PD teams for complex SOCHave an in depth understanding and experience for all Physical Design activities for a large, leading technology SOC ASIC chipHave strong management, technical problem solving, communication and presentation skillsGreat team player able to effectively interact and collaborate with partner teamsExperienced with Front-End design, DFX and Physical Design FlowsCommunication skills : excellent oral, written and presentation skillsExtensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedhawkPhysical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM / IRHands on experience on 7nm and sub-7nm projectsExperienced in Full Chip Floorplaning, PNR Partitioning / Bump Placement is preferredExperience in Low power and high performance design.Responsible for on-time delivery of block-level layouts with exceptional quality.Strong self-driving ability & problem-solving skills with high drive for improvementsShould have excellent communication skills (both written and oral)ACADEMIC CREDENTIALS :
BE / B.Tech / ME / M.TECH or equivalent ECE / EEE
7+ years of experience in Physical Design with atleast 2+ years of experience in people management
Contact : Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : muday_bhaskar@yahoo.com