Senior Staff Design Engineer

Company Description

Incubated at IIT-Hyderabad in 2016, WiSig Networks is located in the heart of Hyderabad. With over 100 researchers and engineers, the company leads in the development and licensing of 5G intellectual property. WiSig Networks collaborates with semiconductor and processor companies to create reference platforms for 5G technologies and licenses its designs and software to original equipment manufacturers. Additionally, the company partners with ecosystem allies to deploy wireless communication equipment, consumer, and IoT devices. WiSig aims to become a global leader in wireless technology and systems, with expansions into 6G technologies.

Exp Level 7+Years

Job Role Description

This full-time on-site role in Hyderabad is for a Staff Design Engineer. The engineer will be responsible for conducting formal and functional verification, RTL design, and debugging of complex digital designs. Daily tasks include working closely with design teams, performing verification planning and execution, and ensuring the high quality and performance of products. Furthermore, the role entails consistently updating validation methodologies and participating in design reviews.

The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top-level systems with emphasis on

verifying the functionality and generating the code / functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage.

Educational Qualification :

• Bachelor major in electronics, embedded programming, ECE, EEE.

Key Requirements :

Architecture exploration and Micro-architecture development

Strong debugging capabilities at RTL simulation and FPGA Emulation.

Note : We are looking for candidates with relevant work experience. Freshers are not eligible for this position, and fresher profiles will not be considered.

Skills Required

FPGA Design, C, Bash, Uvm, code coverage , AMBA, Axi, APB, Perl, Verilog, AHB, System Verilog, Python, Tcl