Greeting from LeadSOC Technologies_ Hydarabad
Role : Post Silicon Validation Engineer
Experience : 3 – 8 years
Location : Hyderabad, On-site
Notice Period : Immediate Joiners
Responsibilities :
- FPGA Design Flow & Validation
- RTL Design, Implementation, and Protocols (PCIe, Ethernet, DDR4 / 5, Memory)
- Integration-focused role : 80% Integration, 20% Design
- System-level Testing & Design
- Silicon Validation
- Debugging Interfaces and Design-level Debugging
- Board-level Debugging (20 : 80 simple design & debug split)
Requirements :
Strong knowledge in RTL design and implementationExpertise in FPGA design flow and validationExperience with system-level testing and silicon validationHands-on exposure to debugging (board level & design level)Familiarity with Xilinx / Intel toolchainsUnderstanding of protocols : PCIe, Ethernet, DDR4 / 5, MemoryRegards'
Murali