Lead Engineer

Role : PD LeadExperience : 7+yrsLocation : BangaloreTechnical Skills : Should be able to handle Full chip PnR (timing / congestion / CTS issues), understanding of IO ring, package support, multi voltage designDeep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR / EM checks and signoff DRC / LVS closureResponsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFMMust have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM)Well versed with the timing closure (STA), timing closure methodologiesGood Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verificationExperience in lower tech node ( Good automation skills in PERL, TCL and EDA tool-specific scriptingAble to take complete ownership for Block / sub-system for complete execution cycleOut of box thinking to meet tighter PPA requirements