Sr RTL Principal Design Engineer (3 Days Left)

Position Requirements :

• BE / BTech / ME / MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
• 8-16 years of core RTL Design experience using Verilog is a must.
• System Verilog experience and experience with UVM based environment usage / debugging is required.
• PCIe / CXL / IDE experience is needed. Prior experience in implementation of complex protocols is a must.
• Prior experience in IP development teams would be an added advantage.

Scripting knowledge is an advantage