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CPU Physical Design CAD Engineer

CPU Physical Design CAD Engineer

ConfidentialBengaluru / Bangalore
30+ days ago
Job description

General Summary

NUVIA, now a part of Qualcomm, is on a mission to reimagine silicon and develop computing platforms that redefine industry standards. We're building custom CPUs that lead the industry in power, performance, and scalability. As a CPU Physical Design CAD Engineer , you will be instrumental in developing and supporting advanced implementation tools and flows that ensure our silicon achieves best-in-class Power, Performance, and Area (PPA).

This is a unique opportunity to work alongside some of the most talented engineers in the world, driving cutting-edge innovations in physical design and EDA tooling.

Minimum Qualifications

  • Bachelor's degree in Computer Science, Electrical / Electronics Engineering, Engineering, or a related field and 6+ years of hardware engineering experience
  • OR
  • Master's degree in a relevant field and 5+ years of experience
  • OR
  • PhD in a relevant field and 4+ years of experience

Roles and Responsibilities

  • Develop, integrate, and release new features in high-performance place-and-route CAD flows
  • Architect and recommend methodology improvements to optimize power, performance, and area
  • Maintain and debug implementation flows , resolving project-specific issues
  • Collaborate with global CPU physical design teams, offering methodology guidance and tools / flow support
  • Partner with EDA vendors to define roadmaps and resolve tool issues
  • Preferred Qualifications

  • Bachelor's or Master's degree in Electrical / Electronics Engineering or Computer Science
  • 10+ years of hands-on experience in place-and-route for high-performance chips, either in CAD or design roles
  • High proficiency in Tcl and Python scripting
  • Experience in automation of CAD and physical design tasks
  • Familiarity with a broad range of Physical Design tasks , including place-and-route, timing analysis, and physical design verification (PDV)
  • Experience working with advanced technology nodes (e.g., 5nm and below)
  • Strong understanding of digital design, timing analysis, and physical verification
  • Proficient with industry-standard tools such as Cadence Innovus
  • Demonstrated success in managing and regressing place-and-route flows
  • Skills Required

    Sta, Python, Timing Analysis, Digital Design, Physical Design, Physical Verification, Tcl

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