RTL Architect

Experience : 8 to 15 years

Expertise :

• Strong understanding of the design convergence cycle, including architecture, micro-architecture, Verification, Synthesis and timing closure.
• Expertise in managing IP dependencies, as well as planning front-end design tasks.
• Design and development of high-speed serial IO protocols
• Implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, low power modes
• Experience in CPU, bus fabrics, or coherence / noncoherent NOC domains is highly desirable.

Skills :

Minimum Qualifications :

Regards,

Puja Saha

Skills Required

BUS Protocols, Peripherals, Verification, Synthesis, formal verification, Timing Closure, Microprocessors, Test Plans, memory controllers