Lead Design Engineer

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description :

• IP Integration and release Engineer for  SSG IP Release engineering  team.
• Position is based in  Bangalore  .
• The role would include IP integration, verification, and release of the IP solution of Cadence to different customers.
• The work involved will be working with the existing RTL, integration of the PHY and controller to create the sub-system, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
• Proficient in ASIC development flows like Lint / CDC / Synthesis (preferably with Genus) / STA. Ability to debug and setup new flows.

Position Requirements :

Scripting knowledge is an advantage.

We re doing work that matters. Help us solve what others can t.

Role :   Design Verification Engineer

Industry Type :   IT Services & Consulting

Department :   Engineering - Hardware & Networks

Employment Type :   Full Time, Permanent

Role Category :   Hardware

Education

UG :   B.Tech / B.E. in Production / Industrial

PG :   M.Tech in Electronics / Telecommunication

Key Skills

Design verification Release engineering ASIC Usage VLSI System verilog PCIE RTL UVM Scripting

Skills Required

Design Verification, System Verilog