BE / B.Tech in ECE / M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal VerificationVery Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocksVery Good experience in Analog Mixed Signal verification simulation toolsGood experience in System Verilog, UVM methodologiesAble to train the team members and guide them to the solutions for problemsGood experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch.Good experience in Gate level netlist simulationExperience in Python, Perl, Shell scripting is added advantage.Good communication and documentation skillsSkills Required
Perl, Shell Scripting, System Verilog, Python, Verilog AMS