Design Engineers

Memory & STA Engineers Experience : 5 years

Location : Bangalore

5-8 years of experience in VLSI layout design or ASIC design. In-depth proficiency in deep sub-micron FinFET technologies 2nm, 3nm, 5nm, 7nm, 10nm, 14nm is strongly desired. Good understanding of the standard cell library development & architecture, ASIC design flow, semi-custom design flows and physical verification tools. Proficient in DRC, LVS, ERC, Density cleanup and also worked on DFM checks Litho, PM.

Automation.

Proficiency in skill, perl, shell scripting.

Interested,please drop your updated resume to janagaradha.n@acldigital.com