Senior Principal DFT Engineer

The Role

Job Description :

Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test / characterization on ATE.

Responsibilities :

Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.

Required Skills and Experience :

• This role is for a Senior Principal DFT Engineer with 16+ years of experience in Design for Test
• Experience coding Verilog RTL, TCL and / or Perl
• Proficient in Unix / Linux environments
• Core DFT skills considered for this position should include some of the following : Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG / IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
• Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field

“Nice To Have” Skills and Experience :

In Return :

We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding.