Responsible for design leadership and development of ultra-high performance, low noise analog solutions associated with mixed signal ICs from initial concept, until production ramp, including design for : manufacturability, yield, test, and reliability.
Performs and supervises detailed design, simulation, verification and validation of integrated circuits.
Directs and supervises block-level and top-level layout activities to ensure optimum circuit performance.
Expert level knowledge and experience designing for system / application level concerns, including : packaging, parasitic, power, die size, cost, etc.
“Power User” level knowledge of SPICE / Spectre testbench creation and simulations, including : PVT, Monte Carlo, mixed signal, modelling, optimization, etc.
Provides positive internal team leadership and communication, coordination of design requirements and trade-offs, and preparation for weekly meetings (internal and customer).
Analog design subject matter expert level communication with customer (and / or marketing), including : presentation in design reviews, representing the analog design team on weekly conference calls, defining / tracking / working to ensure schedule adherence, interactive problem solving, and customer communication under pressure, etc.
Highly creative problem solver, able to generate innovative, new next-generation IP and file patents
Generation of detailed relevant documentation, including : architectural / concept reviews, design gate reviews, internal design documents, test requirements, etc.
Profile description :
Master’s degree in Electrical Engineering with 8 years of experience or PhD with 5 years of experience, with an emphasis in analog / mixed signal Integrated Circuit Design.
Experience with technical leadership in mixed signal IC Design, block level specifications, simulation, modelling, optimizing layout for performance, etc.
“Expert level” transistor-level design knowledge and experience of standard analog building blocks, including Bandgap references, current references, OPAMP, LDO, charge pumps and such for ultra-low noise performance in CMOS processes. Design experience in ADC is a plus
Excellent communication skills (both oral and written) are required, as customer-level technical interface and design / team leadership are necessary under high-pressure situations.
Experience with relevant CAD tools (including Cadence Virtuoso, SPICE, etc.)
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Senior Design Engineer • Delhi, India
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