5+ years experience in ASIC Physical design and flow development
Experience with all aspects of ASIC physical design, including floor planning, power-distribution, multi-voltage design, placement, CTS, and routing, timing
Strong TCL / Python scripting skills. Candidate should have experience in managing, and regressing P&R flows.
The candidate should be familiar with Physical verification and signoff checks
Technology nodes : 2nm to 10nm TSMC or Global Foundry
Tools : Synopsys and Cadence
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