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ASIC - SoC Design Verification
ConfidentialBengaluru / Bangalore24 days ago
Job descriptionCollaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM / OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench / SoC verification environment. Good understanding of SoC RESET / CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS / Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills
PREFERRED EXPERIENCE :
- Proficient in SoC / sub-system / IP level ASIC verification
- Proficient in debugging RTL code using simulation tools
- Experienced with Verilog, System Verilog, C, and C++
- Worked on any High Speed Interface like PCIE / DDR / USB / Other, Good understanding of AXI / AHB / APB Bus protocol
- Prior knowledge of ARM / RISC Processor based designs verification and bring-up verification
- Developing UVM based verification frameworks and testbenches, processes and flows
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience : Perl, Python, Makefile, shell preferred.
Skills Required
Asic, Risk, Ethernet, Soc, Firmware, Arm, Automation
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Design Verification • Bengaluru / Bangalore