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Design Verification Engineer - UVM / RTL Design
Savantis Solutions India Pvt.Ltd.Bangalore27 days ago
Job descriptionDesign and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Bachelor's degree in electrical engineering, Computer Engineering, or a related field (master's degree a plus) 5 - 7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment
Role : Design and Verification Engineer
Experience : 5+ Years
Location : Bangalore
Mode : Full time
Job Description :
- Develop and implement comprehensive verification plans using industry-standard methodologies (e.g.,
UVM)
Qualifications :
(ref : hirist.tech)
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Design Verification Engineer • Bangalore