Incise Infotech - Static Timing Analysis Engineer - VLSI

Immediate Joiners Preferred

About the Role :

Incise Infotech Limited is expanding its VLSI Design team and is looking for skilled Static Timing Analysis (STA) Engineers to contribute to high-performance chip design projects.

This role is ideal for engineers passionate about full-chip timing closure, constraint development, and timing verification in advanced technology nodes.

Key Responsibilities :

• Perform Static Timing Analysis at both block and full-chip levels using industry-standard tools such as PrimeTime or Tempus
• Analyze and debug setup, hold, transition, and other timing violations
• Work closely with RTL, Synthesis, and Physical Design (PD) teams to drive timing closure
• Develop, validate, and manage SDC constraints for various design stages
• Ensure timing sign-off readiness by generating and reviewing timing reports
• Innovate and automate STA flows for improving efficiency and quality of results
• Collaborate with design teams to support tape-out schedules and quality metrics
• Perform PPA (Power, Performance, Area) analysis and support ECO timing closure
• Support multiple projects by providing STA inputs during design reviews

Required Skillsets

(ref : hirist.tech)