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Senior ASIC Verification Engineer - UVM / System Verilog

Senior ASIC Verification Engineer - UVM / System Verilog

Swedium Global ServicesDelhi, IN
10 days ago
Job type
  • Remote
Job description

About Us :

Swedium Global Services is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Job Role : Senior ASIC Verification Engineer

Job Description :

  • Take part of the verification of designs, whether at the block or subsystem level.
  • Participate in defining and implementing UVM-based test environments.
  • Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans.
  • Develop, run, and debug test cases to ensure design quality under supervision.
  • Contribute to the improvement and optimization of verification methodologies.
  • Generate documentation throughout the verification lifecycle.
  • Collaborate closely with other verifiers, designers, and architects.
  • Build competence in the technical domain.
  • Engage in cross-team collaboration to ensure successful project delivery.

Required Qualifications :

  • Bachelor s degree in electrical or computer engineering.
  • 7+ years industry experience in ASIC IP verification using System Verilog and UVM.
  • Strong experience in / with :

    • 1. Development of verification test plans and create directed / randomized test cases.

    2. Formal verification.

  • In implementing scoreboards, checkers, bus functional models in existing testbench environment.
  • Ethernet and PCIe experience
  • AMBA-based designs such as AXI and CHI.
  • SystemVerilog Assertions.

    • (ref : hirist.tech)

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