Division : Artificial Intelligence Solutions Employment Status : Exempt Salary Grade : 110 Shift : Please be aware that if you are selected to formally interview for an internal position you will be required to notify your current manager. Please refer to the Employee Transfers Guidelines posted on Skylink.
Description
Responsibilities
- Digital design specification, design, analysis, and HDL (Verilog) coding
- Behavioral modeling of analog and mixed signal circuits
- Digital back-end : synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc.
- Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models / RTL, firmware, and behavioral models. Test bench development
- Validation of silicon functionality, behavior, and performance
Required Experience and Skills
Master's with 7-10 years of IC design experience or PhD with 4-6 years of IC design experienceStrong motivation to contribute to all facets of chip design from conceptualization to release to productionWorking knowledge of digital IC circuit design in an HDL synthesis environmentWorking knowledge of digital verification and testing techniquesGood verbal and written communication skills, positive attitude, desire to learn, and willingness to work on a teamWorking knowledge of UNIX operating systemsAdditional skills (one or more of these are highly desirable) :
Experience with digital design at geometries ranging from 130-40 nmExperience with digital IO interfaces such at I2C, SPI, etc.Competence in high-level languages (e.g. Matlab, C), scripting languages (e.g. Tcl, Perl, Python, SKILL), and version control systems (e.g. SVN, SOS)Working knowledge of System Verilog and / or UVMExperience leading a team of digital designers, either formally or informallyExperience with embedded processor design and firmware / software development, especially for 8051 or ARM coresCompetence in exploring digital and firmware system / architecture trade-offs such as memory size (ROM, RAM, FLASH, OTP, cache), clock speed, multiple clock domains, and the necessity for dedicated logic and DSPExperience with memory generators and MBISTLow power design and implementation techniquesFamiliarity with DSP techniques and algorithmsExperience with Phase-locked-loops, Frequency Synthesizers or CDR circuits.Desired Experience and Skills