Ip / Soc Verification Engineer
ACL DigitalGandhinagar, Republic Of India, IN21 hours ago
Job description4 to 15+ years of experience in Design Verification (IP / Sub-System / SoC) . Strong proficiency in SystemVerilog and UVM methodology . Solid understanding of verification concepts and debugging techniques . Experience in C-based SoC Verification . Proficiency with tools such as Xcelium, VCS, vManager, and Certitude . Strong scripting experience (Shell, Perl, Python). Experience in Trace and Debug . Low-power (UPF) verification experience is mandatory . Experience with slow-speed peripherals (SPI, UART, I2C, etc.). Exposure to RISC-V-based SoC verification is a plus. Familiarity with Specman / e-based or Mixed-language testbenches is desirable. Experience in CPU or Protocol Verification (PCIe, I2C, CSI2, LVDS, etc.). Knowledge of Digital Signal Processing (DSP) and Digital Filters . Exposure to automotive-grade verification standards . Experience with Jira / Jama for project and issue tracking. Strong ownership and accountability. Excellent problem-solving and debugging abilities. Good communication and collaboration skills. Ability to work independently and within cross-functional teams. Work Type : Hybrid Location : Bangalore / Hyderabad Notice Period : Strictly less than 30 days
Job Title : IP / SS / SoC Verification Engineer (Hybrid – Bangalore / Hyderabad)
Experience : 4 to 15+ years
Notice Period : Strictly less than 30 days
Work Type : Hybrid
Location : Bangalore / Hyderabad
Job Description
We are looking for talented SoC Verification Engineers with strong expertise in SystemVerilog / UVM , solid debugging skills, and a deep understanding of verification methodologies. The role involves hands-on contribution to IP, Sub-system, and SoC-level verification and end-to-end ownership of verification deliverables.
Key Responsibilities
- Develop and execute SystemVerilog / UVM-based verification environments for SoC and IP-level designs.
- Create and maintain verification plans , testbenches, and functional coverage models .
- Perform RTL and Gate-level debugging using industry-standard tools.
- Collaborate with design and architecture teams for feature understanding and issue resolution.
- Lead test planning, task assignment, progress tracking, and delivery of verification tasks.
- Drive coverage closure, regression management, and maintain documentation.
Required Skills
Preferred Skills
Soft Skills
Additional Information
Referral / Contact Details
If you have the required skill set as per the JD or know someone who fits the role, please apply or refer suitable candidates to :
📧 Email : prabhu.p@acldigital.com
📱 WhatsApp : +91 87543 87484
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Verification Engineer • Gandhinagar, Republic Of India, IN
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