The role generally entails a mixture of :Ownership of a piece of the test benchPlanning & execution of feature additions and mode re-enablement on particular variantsBug fixesDebug of regression signaturesDeveloping / Deploying new tools for performance validationPerformance monitor and profiler development and deploymentWorkload specific simulations on the emulatorFollowing skillset is required :Strong Python, C++ skillsReading Specs and developing test plansMonitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolvedCandidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening6 months - 1 Year of industry experiences in the following areas : -Basic of digital design concepts, fifo etcBasic understanding of DDR is a plusUnderstanding of interconnect protocols like AHB / AXI / ACE / ACE-LiteUnderstanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualizationMinimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer EngineeringCandidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding .Minimum Qualifications :
Associate's degree in Computer Science, Electrical / Electronic Engineering, Engineering, or related field.
Skills Required
Ddr, Axi, Verilog, Debug, AHB, Python, Associate Engineer