You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES :
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE :
Industry experience in IP / SOC level design verificationHave worked upon atleast one full cycle of SoC Verification flowStrong SV / UVM, UVC, Scoreboards, Functional coverage, SV assertions, C / C++ expertiseAble to create APIs for SOC level test bench stimulus.Strong debug expertiseMust have good communication skills and ability to work in a team environment.Experience in data path verification protocol like PCIe / CXL / AXI / SATA at SoC LevelExperience in driving task independently and complete with excellent qualitySkills Required
Soc, C++, Pcie, Sata, Firmware, Uvm, Test Planning