Senior RTL Design Engineer-Barcelona

RTL Engineers

Description

We have multiple open positions in our RTL team and we're looking for individuals with either a strong RTL or a strong architecture / microarchitecture background interested in working in several areas of a RISC-V design for an advanced technology node. In particular, areas of focus will be the processor pipeline, d-cache, i-cache, the l2-pipeline and a custom memory controller. We believe in very “vertical” engineers that fully understand the problem to be solved and can take it down to RTL level.

What we offer?  Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)

Requirements

• Minimum Bachelor's degree in computer science
• 8 years in the role
• Knowledge in Verilog
• Scripting