Chief DFT Engineer Specialist
beBeeDftengineerMalappuram, Kerala, India21 hours ago
Job descriptionDevelop and drive DFT strategy and architecture for multiple ASIC / SoC projects. Lead implementation and verification of DFT features such as scan insertion and compression (e.g., EDT), ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1 / 1149.6), IJTAG (1687). Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up. Collaborate with RTL, STA, PD, and test engineering teams for seamless integration. Perform pattern generation, fault simulation, and debug test coverage gaps. Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery. Support silicon bring-up, test vector validation on ATE, and yield optimization. Mentor and guide junior DFT engineers; conduct design reviews and training sessions. Develop and maintain DFT automation scripts and infrastructure. B.E. / B.Tech or M.E. / M.Tech in Electronics, Electrical, or VLSI Design. Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan. Hands-on experience with DFT tools such as Synopsys : DFT Compiler, TetraMAX, TestMAX, Siemens EDA : Tessent ScanPro, MBIST, IJTAG, Cadence / others : Modus, Encounter Test. Strong knowledge of RTL design, STA, and synthesis flows. Proficient in scripting languages (Python, Perl, Tcl) for flow automation. Deep understanding of silicon test challenges and test coverage improvement. Strong leadership, team collaboration, and communication skills.
Expert in Digital Fault Tolerance Engineering
About the Position :
- We are seeking a skilled Chief DFT Engineer to oversee digital fault tolerance engineering, planning, and implementation across complex SoC / ASIC designs.
- The ideal candidate will have 7+ years of experience in DFT for complex ASIC or SoC designs.
Key Responsibilities :
Required Skills and Experience :
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Dft Engineer • Malappuram, Kerala, India
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