Full-Chip Implementation Engineer
LeadSoc Technologies Pvt LtdBengaluru, Republic Of India, IN2 days ago
Job descriptionPerform static and dynamic power analysis at the chip level. Execute end-to-end Netlist-to-GDSII implementation at the full-chip level. Manage hierarchical chip planning , block-level constraints, block integration, and chip finishing. Drive MMMC optimization and closure at top level. Perform clock tree synthesis (CTS) and advanced full-chip clock design. Achieve top-level timing closure using signoff STA in MMMC with crosstalk and OCV considerations. Develop and execute top-level ECO strategies for RTL, netlist, and timing-level changes. Build and customize implementation methodologies based on specific design needs. Debug complex implementation issues and optimize flows for power, performance, and area (PPA) . Automate design flows using Perl / TCL scripting . Provide technical leadership , mentor junior engineers, and ensure timely team deliverables. Collaborate effectively with cross-functional teams including RTL, DFT, STA, and packaging. Strong hands-on experience with FC / ICC / Innovus for implementation. Signoff tool exposure in : DRC / LVS : Calibre Timing signoff : PrimeTime Power integrity analysis : Apache RedHawk Strong debugging abilities and a deep understanding of reference flows. Excellent interpersonal and communication skills. M.E. / M.Tech in Electronics / Electrical Engineering or equivalent. 3–10 years of experience in Physical Design (multiple roles available). Must have worked as technical lead on at least 2 projects . Experience in 28nm and below , preferably 20nm and below technology nodes.
Physical Design Engineer
Job Summary
We are looking for an experienced Physical Design Engineer with strong hands-on expertise in chip implementation from Netlist to GDSII . The ideal candidate will have contributed to at least 5 tape-outs at the top level or hierarchical top level and have prior experience leading physical design teams. Experience in 28nm and below technologies (preferably 20nm and below ) is required.
Key Responsibilities
Top-Level & Hierarchical Physical Design
- Perform top-level die size estimation, floorplanning, power estimation, and power planning .
- Handle IO planning , package compatibility, and signoff.
- Drive ESD analysis on IO rings and ensure complete signoff.
- Conduct netlist and constraint sign-in checks and validation.
- Set up the design implementation environment for full-chip execution.
Power, Timing & Implementation
Methodology & Flow Development
Leadership & Collaboration
Required Skills & Tool Expertise
Qualifications
Experience Level : - 3yrs to 10yrs
Notice Period : - Immediate to 60 Days
Work Location : - Bangalore
Mode of Work : - WFO
Employment Type : - Permanent
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Implementation Engineer • Bengaluru, Republic Of India, IN
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