FPGA Verification Lead

Scope of work

• Lead and own the RTL verification of FPGA-based designs from concept to tape-out
• Define and drive FPGA verification plans and testbenches (System Verilog / UVM).
• Collaborate with design engineers to understand architecture and micro-architecture specifications
• Perform functional coverage analysis, regression testing, and debug failures.
• Mentor and lead verification engineers.

Domain Expertise

Skills Required

Python, Perl, Tcl, systemverilog, Uvm, Vcs