SoC Design Verification Lead

PREFERRED EXPERIENCE :

• Proficient in SoC / sub-system / IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches
• Experienced with Verilog, System Verilog, C, and C++
• Worked on any High Speed Interface like PCIE / DDR / USB / Other, Good understanding of AXI / AHB / APB Bus protocol
• Prior knowledge of ARM / RISC Processor based designs verification and bring-up verification
• Developing UVM based verification frameworks and testbenches, processes and flows
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Scripting language experience : Perl, Python, Makefile, shell preferred.

Skills Required

Python Scripting, SOC design, SoC Verification, System Verilog