Lead Engineer - Formal Verification

Position Overview

We are looking for a Lead Engineer in SoC Verification to join our team and contribute to the Formal Property Verification (FPV) and Connectivity Verification of complex SoC designs.

The engineer will be responsible for developing, executing, and maintaining formal verification strategies to ensure exhaustive property coverage, structural correctness, and architectural compliance across critical blocks and subsystems.

This role requires strong expertise in formal methodologies, hands-on experience with industry-standard formal tools, and the ability to collaborate closely with RTL design, architecture, and full-chip verification teams to ensure first-pass silicon success. The position aligns with core verification competencies expected within the organization for mid-senior technical roles.

Key Responsibilities

Formal Property Verification (FPV) Ownership

• Develop, implement, and execute block-level and subsystem-level formal verification plans.
• Write, qualify, and maintain SystemVerilog Assertions (SVAs) and formal properties ensuring full functional intent is captured.
• Drive property convergence, coverage closure, and modeling of constraints and abstractions needed for formal completeness.
• Analyze unreachable or failing properties and work with design and architecture teams to refine specifications or fix design issues.

Connectivity and Structural Verification

Collaboration With RTL, Architecture & Full-Chip Verification Teams

Debug & Issue Resolution

Tool, Infrastructure & Automation

Documentation & Technical Communication

Qualifications

Preferred Qualifications

Why Join Us

About Us :

L&T Semiconductor Technologies is a leader in innovative semiconductor solutions, committed to pushing the boundaries of technology to create a smarter, more connected world. We are an equal-opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees